Generally, a semiconductor memory device may be classified into a volatile memory device such as a dynamic random access memory (DRAM) and a static random access memory (SRAM) that loses data with the passage of time, or a non-volatile memory device such as a flash memory that continuously possesses data regardless of the passage of time. Since the data inputted into the non-volatile memory device is maintained regardless of the passage of time, the flash memory into which the data is electrically inputted and from which the data is electrically outputted has been widely used in current semiconductor memory devices.
The flash memory includes a memory cell in which the data is stored. The memory cell has a stack type gate structure that includes a tunnel oxide layer on a silicon substrate, a floating gate on the tunnel oxide layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer. Inputting the data into the flash memory is carried out by selectively applying a voltage to the control gate and the substrate to charge electrons in the floating gate. Also, outputting the data from the flash memory is carried out by selectively applying a voltage to the control gate and the substrate to discharge electrons from the floating gate. Here, the dielectric layer functions in maintaining the electrons charged in the floating gate and also transmitting the voltage applied to the control gate to the floating gate.
FIG. 1 is a cross sectional view illustrating a conventional flash memory in a word line direction. Referring to FIG. 1, a tunnel oxide layer 12 and a floating gate 14 are stacked on a substrate 10 having an isolation layer pattern 11. A dielectric layer 16 is formed on the floating gate 14. A control gate 18 is formed on the dielectric layer 16. To induce more of a voltage applied from the control gate 18 to the floating gate 14, maintaining a high coupling ratio between the floating gate 14 and the control gate 18 is required. To achieve the above, the dielectric layer 16 has a thinner thickness so that the dielectric layer 16 has an increased capacitance. Also, the dielectric layer 16 has a charge retention characteristic for preventing the leakage of electrons charged in the floating gate 14. Forming a thin thermal oxide layer on the floating gate 14 including doped polysilicon is very difficult and also causes an increase of a leakage current so that an oxide/nitride/oxide (ONO) layer having a dielectric constant higher than that of an oxide layer is used as the dielectric layer 16.
However, since the floating gate 14 has sharp edge portions A, as shown in FIG. 2, portions of the dielectric layer 16 on the edge portions A of the floating gate 14 have a thickness relatively thinner than that of other portions of the dielectric layer 16. This may cause an inferior distribution of the coupling ratio due to a capacitance distribution of a memory device. Further, since an electric field is concentrated on the sharp edge portions of the floating gate 14, the leakage current is increased so that endurance and data retention of the memory cell may be deteriorated.
The above problems may be generated in forming the dielectric layer 16 having the thin thickness by a chemical vapor deposition (CVD) process in replace of the thermal oxidation process. To overcome the above problems, methods of forming floating gates having rounded edge portions exposed from a substrate are disclosed in Korean Patent No. 0396473 and U.S. Pat. No. 6,387,756. However, according to these methods, the edge portions of the floating gate may not have a completely rounded structure. Also, as shown in FIG. 2, the floating gate is partially removed by a width R in an etching process for forming the rounded structure so that the coupling ratio of the non-volatile memory device may be decreased.